The present invention relates generally to communications systems, and more particularly to a system and method for generating a clock signal using a greatest common measure of sampling frequencies.
A coder/decoder (“codec”) is considered to be any technology that encodes or decodes a signal. For example, telephone companies use codes to convert binary signals transmitted on their digital networks to analog signals converted on their analog networks. As used in the audio field, the audio codec requires a base clock signal for audio sampling. For example, common audio sampling frequencies typically range from 8 KHz to 96 KHz, with 44.1 KHz and 48 KHz listed among the common sampling range. In practical applications, real device frequencies are multiplied by 512 or 64 times the sampling frequency used.
Standard Universal Asynchronous Receiver Transmitter (UART) devices often used for asynchronous or other serial communications, can use a multiplier of 16 times the baud rate is required. The UART controller is often employed as a component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.
FIG. 1 shows an example of various target clocks that can be required by a system on chip (SoC) that employs devices operating at audio sampling frequencies and UART device frequencies. Column 102 lists an exemplary purpose behind the frequency to be generated by the target clock listed in column 104, e.g., audio sampling rate or baud rate. As previously stated, the multiplying factors are typically 512 or 64 for audio sampling and 16 for baud rate. Column 106 lists the multiplier values corresponding to the respective target clock frequencies. The resultant output clock values in column 108 correspond to the multiplied target clock. Column 110 denotes whether the frequency in column 108 can be derived from another clock frequency. As shown in FIG. 1, there are three clock frequencies that are not derived from the other frequencies, these are 49.152 MHz, 45.1584 MHz and 14.7456 MHz. It will be appreciated that the first two values commonly correspond to audio sampling frequencies, while the latter correlates to a serial communications rate. For example, 45.1584 MHz corresponds to a target clock frequency of 88.2 KHz. The remainder of the clock frequencies may be arrived at by dividing one of the three non-derivable frequencies.
A common method for generating three clock signals is by using of two phase-locked loop (PLL) circuits to produce the frequencies where one of the PLL's generates two frequencies by employing a frequency divider. A problem with using this approach is that the use of two phase-locked loop circuits uses more space than would a system using only one phase-locked loop circuit.
An alternative approach to generating all of the frequencies listed in FIG. 1 is the use of a single input frequency and a simple divider. However, such an input frequency would be the greatest common measure of the three non-derivable clocks, which for the example of FIG. 1 is 7,225,344,000 Hz (7.225344 GHz). It is often desirable to use lower speed clocks because they are more readily available. Furthermore, lower speed clocks consume less power and generate less heat.
Thus there exists a need for a method and system to simplify the internal generation of a multiple clock signals. Furthermore, there exists the need to minimize the space utilized by the clock generator.